Lemonergy · Studio block

Rate transition

Samples a whole input at its declared period and holds the complete value between instants on the deterministic simulation clock.

Behavior

y(t) = u(tₖ), tₖ ≤ t < tₖ₊₁.

Original Lemonergy interface view. Lines identify ports; they are not a completed simulation circuit.

Ports and observed outputs
Name	Direction	Unit	Meaning
`in0`	input	1	Input; real 3 array.
`out0`	output	1	Held output; real 3 array.

Defaults are initial model values. Select values for your own model and operating conditions.

Configuration fields
Parameter	Unit	Default	Meaning and limits
Sample period `sampleTimeS`	s	0.1	Positive interval between sample instants. Values are held between samples. Minimum 0

Input = [2,4,6]. Held output at 0 s = [2,4,6].

Numerical checks for the bundled synthetic example
Output	Time (s)	Expected value	Unit	Absolute tolerance
Held output `out0`	0	`[2, 4, 6]`	1	1e-09

Rate transition [1]

Rate transition [1]: 2 — at 0 s

11 actual recorded samples. Lines are visual guides between samples. Synthetic example, not measured cell data.

Samples a whole input at its declared period and holds the complete value between instants on the deterministic simulation clock.

Rate transition: y(t) = u(tₖ), tₖ ≤ t < tₖ₊₁.
- Use the block reference for settings and connections.
- Implementation tested locally; public release pending.

Deterministic single simulation clock and a configured output sample grid; no asynchronous task scheduling or thread-race guarantee.

This software operation is defined by its public contract and worked example; no external research result is claimed.

This reference follows the public interface and locally verified numerical checks for an upcoming release.

Contract: Lemonergy Studio public contract · Verification record: verification-2026-10-27